The Future of Computing Performance Game Over or Next Level? (2011) / Chapter Skim
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3 Power Is Now Limiting Growth in Computing Performance
3 Power Is Now Limiting Growth in Computing Performance
Pages 80-104
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From page 80... ...
This chapter argues that such limitations will constrain the computation performance of even parallel computing systems unless computer designers take fundamentally different approaches. The laws of thermodynamics are evident to anyone who has ever used a laptop computer on his or her lap: the computer becomes hot.
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From page 81... ...
In addition, computers are increasingly available in a vari ety of form-factors and many, such as cell phones, have strict power limits because of user constraints. People do not want to hold hot cell phones, and so the total power budget needs to be under a few watts when the phone is active.
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The chapter also discusses why modern scaling produces smaller power gains than before. With that background in technology scaling, the chapter then explains how computer designers have used improving technology to create faster computers.
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. 4 NMOS transistors are lateral devices that work by having a "gate" terminal that controls the surface current flow between the "source" and "drain" contacts.
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Zeller, 1981, A 32-bit VLSI CPU chip, IEEE Journal of Solid-State Circuits 16(5) : 537-542, available online at http://ieeexplore.ieee.org/stamp/stamp.jsp?
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LeBlanc, 1974, Design of ion-implanted MOSFETS with very small physical dimensions, IEEE Journal of Solid State Circuits 9(5)
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Given that description of classic CMOS scaling, one would expect the power of processors to have remained constant since the CMOS transition, but this has not been the case. During the late 1980s and early 1990s, supply voltages were stuck at 5 V for system reasons.
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From page 87... ...
This section briefly describes how those performance improvements were achieved and what contributed to the slowdown in improvement early in the 2000s. To achieve exponential performance growth, microprocessor designers scaled processor-clock frequency and exploited instruction-level paral 12 For older processors, SPEC2006 numbers were estimated from older versions of the SPEC benchmark by using scaling factors.
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per pipeline stage.19 Separating the effect of technology scaling from those of the other improvements requires examination of metrics that depend solely on the improvements in underlying CMOS technology (and not other improve 16 Ibid. 17 Mark Horowitz and William Dally, 2004, How scaling will change processor architecture, IEEE International Solid States Circuits Conference Digest of Technical Papers, San Fran cisco, Cal., February 15-19, 2004, pp.
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: 1702-1711. 3 Mark Horowitz and William Dally, 2004, How scaling will change processor architecture, IEEE International Solid States Circuits Conference Digest of Technical Papers, San Francisco, Cal., February 15-19, 2004, pp.
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Gelsinger, 2001, Microprocessors for the new millennium: Challenges, op portunities, and new frontiers, IEEE International Solid-State Circuits Conference Digest of Technical Papers, San Francisco, Cal., February 5-7, 2001, pp.
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can exploit capabilities of CMOS technology more effectively than single-processor chips.21 However, during the 1990s, the performance of single processors continued to scale at the rate of more than 50 percent per year, and power dissipation was still not a limiting factor, so those efforts did not receive wide attention. As single-processor performance scaling slowed down and the air-cooling power-dissipation limit became a major design constraint, researchers and industry shifted toward CMPs or multicore microprocessors.22 21 Kunle Olukotun, Basem A
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106-107; Marc Tremblay and Shailender Chaudhry, 2008, A third-generation 65nm 16-core 32-thread plus 32-count-thread CMT SPARC processor, IEEE International Solid-State Circuits Conference Digest of Technical Papers, San Francisco, Cal., February 3-7, 2008, p. 82-83; Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Michael Abrash, Pradeep Dubey, Stephen Junkins, Adam Lake, Jeremy Sugerman, Robert Cavin, Roger Espasa, Ed Grochowski, Toni Juan, and Pat Hanrahan, 2008, "Larrabee: A many-core x86 architecture for visual computing, ACM Transactions on Graphics 27(3)
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236-243. 24 Mark Horowitz and William Dally, 2004, How scaling will change processor architecture, IEEE International Solid States Circuits Conference Digest of Technical Papers, San Fran cisco, Cal., February 15-19, 2004, pp.
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To understand those issues and their ramifications, we need to revisit technology scaling and look at one aspect of transistor performance that we ignored before: leak age current. As described earlier, CMOS circuits have the important property that they dissipate energy only when a node changes value.
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The height of the barrier is normally called the threshold voltage (Vth) of the transistor, and the leakage current can be written as q(Vgs – Vth )
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While leakage current grew exponentially with shrinking Vth, the contribution of subthreshold leakage to the overall power was negligible as long as Vth values were still relatively large. But ultimately by the 90-nm node, the leakage grew to a point where it started to affect overall chip power.27 At that point, Vth and Vsupply scaling slowed dramatically.
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From page 97... ...
Finding: The growth in the performance of computing systems -- even if they are multiple-processor parallel systems -- will become limited by power consumption within a decade. ADVANCED TECHNOLOGY OPTIONS If CMOS scaling, even in chip-multiprocessor designs, is reaching limits, it is natural to ask whether other technology options might get around the limits and eventually overtake CMOS, as CMOS did to nMOS and bipolar circuits in the 1980s.
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From page 98... ...
. changes and opportunities and to prepare to utilize them (Mark Bohr, 2009, The new era of scaling in an SOC world, IEEE International Solid-State Circuits Conference , San Francisco, Cal., February 9, 2009, available online at http://download.intel.com/technology/ architecture-silicon/ISSCC_09_plenary_paper_Bohr.pdf)
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Devices will have large numbers of these structures, so the voltage must be less than CMOS operating voltages at similar performance. The second issue is performance and reliability.
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Beyond some limit, lowering energy per instruction by processor sim plification can lead to overall CMP performance degradation because processor performance starts to decrease faster than energy per instruc tion. That range is likely to be a factor of about 10, that is, energy per instruction cannot be reduced by more than a factor of 10 compared with the highest-performance single-processor chip, such as the Intel Pentium 4 or the Intel Itanium.34 When such limits are reached, we will need to create other approaches 32 In their article, cited in the preceding footnote, Banerjee et al.
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Figure 3.5 shows data for general-purpose processors, digital-signal processors, and application-specific inte grated circuits (ASICs) from publications presented at the International Solid-State Circuits Conference.
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SOURCE: 3.5 bottom Robert Brodersen of the University of California, Berkeley, and Teresa Meng of Stanford University. Data published at International Solid-State Circuits Conference (0.18- to 0.25-µm)
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Available online at http://www.itrs.net/Links/2007ITRS/Home2007.htm. Kannan, Hari, Fei Guo, Li Zhao, Ramesh Illikkal, Ravi Iyer, Don Newell, Yan Solihin, and Christos Kozyrakis.
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"Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages." In Proceedings of the 35th Design Automation Conference. New Orleans, La.., June 21-25, 1999, pp.
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